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Software Engineer Intern

Cadence Design Systems

Designed algorithms to optimize cross-processor connection latency, accelerating hardware emulation by 10–20%.

Student Researcher

Google

Designed algorithms that parallelize SPICE simulation while pruning unnecessary input patterns to improve in-house timer performance.

Softeware Engineer Intern

Intel

Utilized a constraint analyzer to automate FPGA design debugging.

PhD

University of Wisconsin-Madison

Electrical and Computer Engineering

Master

University of Utah

Entertainment Arts and Engineering

Bachelor

National Cheng Kung University

Computer Science

PathGen: An Efficient Parallel Critical Path Generation Algorithm

IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC)

Ink: Efficient Incremental k-Critical Path Generation

IEEE/ACM Design Automation Conference (DAC)

G-PathGen: An Efficient GPU-parallel Critical Path Generation Algorithm

Designed efficient GPU kernel algorithms for parallel critical path generation and dynamically adjusted the generated path count to maximize GPU utilization while minimizing redundant work.

• GPU-parallel Algorithms
• Critical Path Generation

PathGen: An Efficient Parallel Critical Path Generation Algorithm

Designed a multi-level queue scheduler to efficiently schedule parallel exploration of similar-priority paths.

• CPU-parallel Algorithms
• Critical Path Generation

Ink: Efficient Incremental k-Critical Path Generation

Designed an algorithm that efficiently identifies a set of paths to reuse for the next query and effectively prunes the path search space.

• Incremental STA
• Critical Path Generation